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| IRFR9110, IRFU9110 Data Sheet July 1999 File Number 4001.3 3.1A, 100V, 1.200 Ohm, P-Channel Power MOSFETs These are advanced power MOSFETs designed, tested, and guaranteed to withstand a specific level of energy in the avalanche breakdown mode of operation. These are P-Channel enhancement mode silicon gate power field-effect transistors designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17541. Features * 3.1A, 100V * rDS(ON) = 1.200 * Temperature Compensating PSPICETM Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol D Ordering Information PART NUMBER IRFR9110 IRFU9110 PACKAGE TO-252AA TO-251AA BRAND IF9110 IF9110 G NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in the tape and reel, i.e., IRFR91109A. S Packaging JEDEC TO-251AA SOURCE DRAIN GATE JEDEC TO-252AA GATE SOURCE DRAIN (FLANGE) DRAIN (FLANGE) 4-77 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 IRFR9110, IRFU9110 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRFR9110, IRFU9110 -100 -100 20 3.1 Refer to Peak Current Curve Refer to UIS Curve 25 0.2 -55 to 150 300 260 UNITS V V V A Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg W W/oC oC oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V VGS = VDS, ID = 250A VDS = -100V, VGS = 0V VGS = 20V ID = 1.9A, VGS = -10V VDD = -50V, ID = 4A RL = 11, VGS = -10V RGS = 24 TC = 25oC TC = 150oC MIN -100 -2.0 VGS = 0 to -10V VDD = -80V, ID = 3.1A, RL = 25.8 VDS = -25V, VGS = 0V f = 1MHz TYP 10 27 15 17 290 94 18 MAX -4.0 -1 -50 100 1.200 50 50 8.7 4.1 2.2 5.00 100 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF oC/W oC/W Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate to Drain Charge Gate to Source Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg Qgd Qgs CISS COSS CRSS RJC RJA Source to Drain Diode Ratings and Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovery Charge SYMBOL VSD trr QRR ISD = -3.1A ISD = -4.0A, dISD/dt = -100A/s TEST CONDITIONS MIN TYP 105 0.51 MAX -5.5 160 1.0 UNITS V ns C 4-78 IRFR9110, IRFU9110 Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 ID , DRAIN CURRENT (A) 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 150 Unless Otherwise Specified -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 25 50 75 100 125 150 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 10 0.5 ZJC , TRANSIENT THERMAL IMPEDANCE 1 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC + TC 10-3 10-2 10-1 100 101 0.1 0.01 10-5 10-4 t 1, RECTANGULAR PULSE DURATION (s) FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE -20 -10 ID , DRAIN CURRENT (A) 100s IDM , PEAK CURRENT CAPABILITY (A) TC = 25oC, TJ = MAX RATED -30 VGS = -20V FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT CAPABILITY AS FOLLOWS: 150 - T C I = I 25 ---------------------- 125 -10 1ms -1 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) -0.1 -1 100ms DC VDSS MAX = -100V VGS = -10V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION -1 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) TC = 25oC 100 101 -10 -100 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY 4-79 IRFR9110, IRFU9110 Typical Performance Curves -10 IAS , AVALANCHE CURRENT (A) -7.75 Unless Otherwise Specified (Continued) ID, DRAIN CURRENT (A) EAS = 140mJ CONDITIONS: VDD = -25V, IAS = -3.1A, L = 21mH, STARTING TJ = 25oC STARTING TJ = 25oC -6 -5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC VGS = -20V VGS = -10V VGS = -8V -4 -3 -2 -1 0 VGS = -4.5V VGS = -7V STARTING TJ = 150oC If R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) If R 0 tAV = (L/R) In [(IAS * R) / (1.3 RATED BVDSS - VDD +1] 0.1 1 TAV, TIME IN AVALANCHE (ms) 10 VGS = -6V VGS = -5V -1 0.01 0 -2 -4 -6 -8 -10 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS -10 ID(ON), ON STATE DRAIN CURRENT (A) -8 -55oC NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = -15V 2.0 VGS = VDS , ID = -250A 1.5 -6 25oC -4 150oC 1.0 0.5 -2 0 0 -2 -4 -6 -8 -10 VGS, GATE TO SOURCE VOLTAGE (V) 0.0 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE THRESHOLD VOLTAGE 2.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = -10V, ID = -3.1A NORMALIZED GATE 2.0 VGS = VDS , ID = -250A 1.5 1.5 1.0 1.0 0.5 0.5 0.0 -80 -40 0 40 80 120 180 0.0 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 4-80 IRFR9110, IRFU9110 Typical Performance Curves 400 CISS C, CAPACITANCE (pF) 300 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD Unless Otherwise Specified (Continued) VDS , DRAIN TO SOURCE VOLTAGE (V) -100 VDD = BVDSS -75 RL = 32.2 IG(REF) = -1.45mA VGS = -10V 0.75 BVDSS 0.75 BVDSS 0.50 BVDSS 0.50 BVDSS 0.25 BVDSS 0.25 BVDSS VDD = BVDSS -10.0 VGS , GATE TO SOURCE VOLTAGE (V) -7.5 200 COSS -50 -5.0 100 CRSS 0 0 -5 -10 -15 -20 -25 VDS , DRAIN TO SOURCE VOLTAGE (V) -25 -2.5 0 20 IG(REF) IG(ACT) t, TIME (s) 80 IG(REF) IG(ACT) 0.0 FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer to Application Notes AN7254 and AN7260. FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS RG 0 + VDD VDD 0V VGS DUT tP IAS 0.01 IAS tP BVDSS VDS FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL 0 10% tOFF td(OFF) tf 10% DUT VGS RG VDD + VDS VGS 0 90% 90% 10% 50% PULSE WIDTH 90% 50% FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS 4-81 IRFR9110, IRFU9110 PSPICE Electrical Model .SUBCKT IRFU9220 2 1 3 CA 12 8 723e-12 CB 15 14 733e-12 CIN 6 8 517e-12 DBODY 5 7 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 6 DPLCAPMOD EBREAK 7 11 17 18 -244.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTO 20 6 8 18 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 2.609e-9 LSOURCE 3 7 2.609e-9 MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 1.194 RGATE 9 20 2.17 RIN 6 8 1e9 RLDRAIN 2 5 10 RLGATE 1 9 26.09 RLSOURCE 3 7 26.09 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 90.1e-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 -0.77 ESCL 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/4.6,6))} .MODEL DBDMOD D (IS=2.56e-14 RS=8.09e-2 TRS1=-2.45e-3 TRS2=-1.33e-5 CJO=4.21e-10 TT=1.17e-7) .MODEL DBKMOD D (RS=5.07 TRS1=-1.05e-3 TRS2=1.28e-5) .MODEL DPLCAPMOD D (CJO=170e-12 IS=1e-30 N=10) .MODEL MOSMOD PMOS (VTO=-3.58 KP=1.38 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=1.1e-3 TC2=-2.73e-6) .MODEL RDSMOD RES (TC1=6.95e-3 TC2=2.23e-5) .MODEL RSCLMOD RES (TC1=2.40e-3 TC2=-1.5e-5) .MODEL RVTOMOD RES (TC1=-3.27e-3 TC2=-1.33e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=5.29 VOFF=3.29) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=3.29 VOFF=5.29) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.1 VOFF=-4.9) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.9 VOFF=0.1) GATE 1 LGATE RLGATE RGATE 9 REV 9/6/94 RLDRAIN DPLCAP 10 LDRAIN RSCL2 RSCL1 + 51 5 51 6 8 VTO + 16 21 MOS1 RIN CIN 8 RSOURCE 7 RLSOURCE 3 SOURCE LSOURCE S1A 12 13 8 S1B CA + 6 EGS 8 + EDS 14 5 8 13 S2A 14 13 S2B CB IT 19 VBAT + 15 17 RBREAK 18 ESCL 50 RDRAIN 11 + EBREAK 17 18 MOS2 DBODY DBREAK 5 DRAIN 2 ESG + EVTO 18 20 8 6 - + RVTO - - - .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley. 4-82 IRFR9110, IRFU9110 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 4-83 |
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